Analog-to-digital converters (ADCs) are widely used to process electrical signals in many electronic applications. An integrated circuit analog-to-digital converter typically accepts an analog input voltage signal and converts the signal into a digital form as the output. A modern digital communication system, such as for a cellular telephone base station, for example, may often require an ADC with a high resolution of greater than 12 bits, a bandwidth greater than 200 MHz, and low power consumption and low distortion for improved overall system performance.
A pipelined ADC includes a series of subconverter stages with each stage including a flash analog-to-digital converter, a digital-to-analog converter (DAC) and an interstage amplifier connecting the DAC to an adjacent stage. The last stage typically includes only a flash ADC. A multi-step ADC may include one or more similar subconverter stages which are sequentially reused in generating the digital output signal.
There are several potential error sources in the subconverter stages of an integrated circuit analog-to-digital converter. These errors include offset, noise, DAC and flash ADC errors, and errors in the interstage gain amplifier. The subconverter flash ADC error may be readily corrected, for example, by the use of digital error correction logic circuits. The kT/C thermal noise error source caused in a sampled-data system may be reduced by proper choice of the sampling capacitor size.
Two dominant error sources in a high resolution pipelined or multi-step ADC are the DAC and the interstage amplifier gain errors. To reduce these two errors, a conventional method has been to measure the components that contribute to the errors, and then calculate and implement the calibration. However, the effectiveness of the calibration is often judged by the linearity of the analog-to-digital converter. Although the correlation between the converter linearity and the error contributing components is theoretically close, it is still only an indirect method to achieve good linearity through component measurement/calibration.
U.S. Pat. No. 4,354,177 to Sloane discloses an apparatus and method for exciting the input of an ADC with exponential signals to generate histograms to determine an amplitude probability distribution of each digital output value. The histograms may be processed in a manner which produces the transfer characteristic of the converter under test which is independent of the dynamic characteristics of the excitation signals, thus eliminating the need for accurate knowledge of the parameter values of the testing circuit.
The DAC of an analog-to-digital converter typically includes a resistor ladder network formed by thin film resistors. These resistors may be laser trimmed to reduce the DAC error. However, the interstage gain error is not as readily determined and corrected. In the past, attempts have been made to trim the capacitors or disconnect small value trimming capacitors associated with a switched capacitor interstage amplifier as disclosed, for example, in an article entitled "A 13-b 2.5-MHz Self-Calibrated Pipelined A/D Converter in 3-.mu.m CMOS" by Lin et al. appearing in IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991. Unfortunately, trimming capacitors may be extremely difficult in practice, especially to achieve predictable and accurate results. Predictable results are also very difficult when disconnecting small trim capacitors to calibrate the gain.
Unfortunately, conventional test and calibration circuits, such as disclosed in U.S. Pat. No. 5,266,951 to Kuegler et al., for example, typically require a predetermined frequency or signal level and also require the calculation of calibration values corresponding to the input signal level and slope. Moreover, a large amount of calibration data has to be processed and stored. Similarly, U.S. Pat. No. 4,903,024 to Evans et al. also discloses a calibration method using a Fast Fourier Transform (FFT) to calculate calibration data with respect to the input level and slope. Both systems require a large number of data calculations and storage which therefore greatly slows the cycle time of the calibration. In addition, a highly linear input source is also often required.